Built-in self test (BIST) methodologies are currently used to diagnostically test the logic portions of an IC and typically provide fault coverage on the order of 98% or higher. In a typical partial scan BIST technique, such as that disclosed by A. Kraniewski and S. Pilarski in "Circular Self Test Path: A Low-Cost BIST Technique for VLSI Circuits", IEEE Trans. on CAD, Vol. 8, No. 1, pp. 46-55, January 1989 and incorporated by reference herein, selected ones of the storage elements contained within the target logic circuit are converted into scannable, or BIST, elements and connected together to form a "scan chain." A pattern generator such as pseudo random pattern generator (PRPG) or a weighted random pattern generator (WRPG) is used to provide random vectors as input signals into the scan chain. The resultant output signals generated by the scan chain and circuit outputs in response to the random input vectors are then received by a multiple input signature analyzer (MISR). Using these received output signals, the MISR generates a final value. Faults within the circuit are then detected by comparing this final value with simulation data. Storage elements are selected for conversion to BIST elements such that each logic cycle within the circuit design will be broken, i.e., each cycle will, after BIST conversion, contain at least one such BIST element.
FIG. 1 illustrates the resultant conversion of an ordinary D flip-flop 10 into a scannable or BIST element 12. A logic network including NAND gates 14, 16 and an exclusive OR gate 18 is connected to the input terminal of flip-flop 10. The original input signal D and a first BIST control signal B0 are inputs to NAND gate 14 while a scan input vector and a second BIST control signal B1 are inputs to NAND gate 16. BIST control signals B0 and B1 determine the operating mode of scannable flip-flop 12.
BIST architectures such as that described above are typically inserted into a logic with little or no consideration given to resultant performance degradations. When designing logic circuits, most designers do so such that all functional and timing requirements are initially satisfied and then rely on automatic test tools to insert BIST elements logic into the circuit. If timing delays attributable to BIST elements and logic are ignored, insertion of such BIST elements and logic can adversely affect the timing behavior of the critical paths of the circuit, thereby resulting in critical timing violations. A number of design iterations may be required in the design of the circuit to correct these resultant timing violations. Such iterations are, however, cumbersome and often ineffective since the circuit designer is typically not familiar with changes the circuit netlist resulting from the insertion of BIST elements and logic.
Other attempts to incorporate performance degradation into partial scan BIST methodologies involve statically specifying which flip-flops lie in a critical path before any BIST element insertion so that these "critical" flip-flops are not modified, i.e., converted into BIST elements. The modification of flip-flops not in a critical path may, however, render previously uncritical paths in the design critical, thereby creating a new set of critical flip-flops that, if modified, would result in timing violations. Furthermore, where a large proportion of flip-flops within the target circuit are deemed "critical" and thus not suitable for modification into BIST elements, there may not be enough remaining non-critical flip-flops suitable for such modification to ensure that all logic cycles are broken which, in turn, results in poor fault coverage.
Others so attempting to implement a performance-driven partial scan methodology factor in constant timing delays associated with the BIST elements and logic in determining which flip-flops are suitable to modify into BIST elements. For example, see J. Y. Jou and K. T. Cheng, "Timing-Driven Partial Scan", Proc. ICCAD, pp. 404-407, 1991). Such an approach, however, considers timing delays at the input of BIST elements; additional delays caused at the outputs of BIST elements are ignored. Like those approaches described above which statically exclude critical flip-flops from BIST conversion, that disclosed by Jou and Cheng fails to consider dynamic timing information of the circuit in computing accurate delays introduced by BIST elements and logic and, therefore, does not effectively minimize performance degradation due to the insertion of BIST architectures into a logic circuit.
Therefore what is needed is a partial scan BIST insertion technique that, in addition to minimizing the increase in silicon area and optimizing the fault coverage, dynamically predicts the performance degradation of a circuit resulting from the conversion of storage elements into BIST elements.